1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to the formation of dielectric material layers of reduced permittivity.
2. Description of the Related Art
Semiconductor devices and any other microstructures are typically formed on substantially disc-shaped substrates made of any appropriate material. The majority of semiconductor devices including highly complex electronic circuits are currently, and in the foreseeable future will be, manufactured on the basis of silicon due to the virtually unlimited availability of silicon, thereby rendering silicon substrates and silicon-containing substrates, such as silicon-on-insulator (SOI) substrates, viable carriers for forming semiconductor devices, such as microprocessors, SRAMs, ASICs (application specific ICs) and the like. The individual integrated circuits are arranged in an array, wherein most of the manufacturing steps, which may involve several hundred individual process steps in sophisticated integrated circuits, are performed simultaneously for all chip areas on the substrate, except for photolithography processes, metrology processes and packaging of the individual devices after dicing the substrate. Thus, economical constraints drive semiconductor manufacturers to steadily increase the substrate dimensions, thereby also increasing the area available for producing actual semiconductor devices and thus increasing production yield. On the other hand, device dimensions are continuously reduced in view of performance criteria, as, typically, reduced transistor dimensions provide an increased operating speed.
In modern integrated circuits, the circuit elements are formed in and on a semiconductor layer, while most of the electrical connections are established in one or more “wiring” layers, also referred to as metallization layers, wherein the electrical characteristics, such as resistivity, electromigration, signal propagation delay, etc., of the metallization layers significantly affect the overall performance of the integrated circuit. Due to the ongoing demand for shrinking the feature sizes of highly sophisticated semiconductor devices, copper, in combination with a low-k dielectric material, has become a frequently used alternative in the formation of so-called wiring structures comprising metallization layers having metal line layers and intermediate via layers. Metal lines act as intra-layer connections and vias act as inter-layer connections, which commonly connect individual circuit elements to provide the required functionality of the integrated circuit. Typically, a plurality of metal line layers and via layers stacked on top of each other are necessary to realize the connections between all internal circuit elements and I/O (input/output), power and ground pads of the circuit design under consideration.
For extremely scaled integrated circuits, the signal propagation delay is no longer limited by the circuit elements, for instance by field effect transistors, but is limited, owing to the increased density of circuit elements, which requires an even more increased number of electrical connections for mutually connecting these circuit elements, by the close proximity of the metal lines, since the line-to-line capacitance increases as the spacing decreases. For example, in presently available devices produced by volume production techniques, the distance of neighboring metal lines may be 100 nm and less in some metallization levels. This fact, in combination with a reduced conductivity of the lines due to a reduced cross-sectional area, results in increased resistance capacitance (RC) time constants. For this reason, traditional dielectrics, such as silicon dioxide (k>4) and silicon nitride (k>6-7) are increasingly replaced in metallization layers by dielectric materials having a lower permittivity, which are therefore also referred to as low-k dielectrics having a relative permittivity of approximately 3 or less.
However, in very advanced semiconductor devices with reduced distances between neighboring metal lines, such as the 45 nm technology node, the resulting parasitic RC time constants may still be considered inappropriate, thereby requiring even lower values for a dielectric constant of the inter metal dielectric material. For this purpose, the dielectric constant may further be reduced to values of 2.7 and less, which may also be referred to as ultra low-k (ULK) materials. Thus, great efforts have been made in developing materials and corresponding manufacturing techniques usable in high volume production. For this purpose, a plurality of spin-on processes, in combination with corresponding polymer materials, may frequently be used, while, in other approaches, plasma enhanced chemical vapor deposition (CVD) techniques are considered as promising candidates for providing low-k dielectric materials. For example, in some approaches, the basic dielectric constant of a plurality of CVD deposited low-k dielectric materials may further be reduced by reducing the material density, which may frequently be accomplished by incorporating so-called porogens, i.e., organic materials including methyl groups that may be removed, at least partially, after the deposition so as to produce a porous dielectric material having the desired reduced dielectric constant. For example, a plurality of process techniques have been established in which hydrogen-containing organic silicon materials may be provided to act as a basic low-k dielectric material and thus as a backbone for ULK materials, while, additionally, appropriate precursor species may be incorporated into the deposition ambient during the plasma enhanced CVD process, which may thus be incorporated into the basic low-k dielectric material. After deposition of the low-k dielectric material, a further treatment, such as radiation by ultraviolet light, may be performed to specifically break up chemical bonds of the porogens and to cause out-diffusion of the corresponding modified molecules, thereby generating respective nano voids in the basic low-k dielectric material. Although the deposition of low-k dielectric materials, which may have per se a very low dielectric constant or which may be converted in ultra low-k materials by subsequent treatment, by means of plasma enhanced CVD techniques presents a very promising approach for sophisticated semiconductor devices, it turns out, however, that, in addition to general issues related to dielectric materials of reduced permittivity, such as reduced mechanical stability and the like, deposition-related failures may be observed which may not be compatible with defect criteria of semiconductor devices having critical dimensions of 50 nm and less, as will be described in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 which comprises a substrate 101, which may include any circuit elements, such as transistor elements, capacitors and the like. For convenience, these circuit elements are not shown. The substrate 101 may represent a bulk silicon substrate or an SOI substrate, since, typically, complex integrated circuits produced by volume production techniques may be formed on the basis of a silicon material, as previously explained. Furthermore, a dielectric layer 102, which may be comprised, at least partially, of a low-k material or any other dielectric material, may be formed above the substrate 101, which may represent a portion of a metallization level or a contact structure of the semiconductor device 100. For example, a metal region 103 is formed within the dielectric layer 102 and may represent any highly conductive device area, such as a contact area of a circuit element or a metal region of a metallization layer. The metal region 103 may be separated from the material of the dielectric layer 102 by a barrier layer 104, which is typically provided as a layer for reducing the diffusion of metal atoms into the dielectric material 102 and also to reduce the diffusion of atoms from the dielectric layer 102 into the metal region 103. Furthermore, the barrier layer 104 may also enhance the adhesion of the metal to the dielectric material. In sophisticated devices, the metal region 103 may comprise copper and the barrier layer 104 may be comprised of one or more layers including tantalum, tantalum nitride, titanium, titanium nitride and the like. Moreover, frequently, a dielectric barrier layer or cap layer 105 comprised of a dielectric material that substantially prevents diffusion of metal atoms of the metal region 103 into neighboring dielectric areas is provided, while in other cases, in addition to or alternatively, the layer 105 may have etch stop capabilities during the patterning of a further dielectric layer 106, which may represent a layer of dielectric material having a desired reduced dielectric constant, as described above. For example, the dielectric barrier or cap layer 105 may comprise silicon nitride, silicon carbide, nitrogen-containing silicon carbide and the like, which may efficiently reduce copper diffusion and which may also provide enhanced mechanical integrity and provide the desired etch stop capabilities. It should be appreciated that additional dielectric materials may also be provided between the dielectric layer 102 and layer 106, which may be comprised of a mixture of silicon, oxygen, hydrogen and carbon, possibly in combination with a porogen 107 which may have to be removed, at least partially, at a later manufacturing stage, as discussed above. For example, appropriate “transition” layers may be provided to enhance the adhesion of the dielectric layer 106 to the lower lying device level, if materials of a dielectric constant of 2.5 and less are considered.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. After forming the basic structures of any circuit elements in and above the substrate 101, the dielectric layer 102 and the metal region 103 with a conductive barrier layer 104 may be formed by well-established process techniques. Next, the dielectric barrier or cap layer 105 may be deposited, for instance by plasma enhanced CVD on the basis of well-established process recipes so as to form, for instance, a nitrogen-enriched silicon carbide layer and the like. Thereafter, the dielectric layer 106 may be deposited by a plasma enhanced CVD deposition process 108, in which a plasma ambient may be established by applying an appropriate high-frequency power, i.e., by applying electromagnetic power with a frequency of 10-15 MHz, typically approximately 13 MHz, which may be capacitively or inductively coupled into the plasma ambient. For this purpose, well-established deposition tools are available in which an appropriate plasma may be generated. During the deposition process 108, an appropriate pressure may be adjusted and appropriate precursor gases, such as trimethylsilane (3MS) or tetramethylsilane (4MS), in combination with additional carrier gases, may be supplied to the deposition ambient 108. For instance, nitrogen, ammonium and the like may frequently be used in combination with other specified precursor species so as to form a silicon, carbon and hydrogen-containing material. As previously explained, in the deposition phase of the process 108, an appropriate precursor species for incorporating the porogen 107 may be supplied, if required. A specific set of process parameters for the deposition phase of the process 108 may readily be established by experiment and may depend on the characteristics of material of the layer 106, for instance with respect to the desired value of the dielectric constant, mechanical characteristics, such as hardness and the like. The deposition phase of the process 108 may be stopped by turning off the high frequency power for maintaining the plasma in the ambient 108 and by discontinuing the supply of the corresponding precursor gases. In this manner, a desired thickness of the layer 106 may be provided for a given deposition rate during the deposition phase of the process 108. Thereafter, residues of the precursor species may be removed from the ambient 108 and finally a purge step may be performed, for instance at the pressure of 3-10 Torr on the basis of appropriate inert gases, which are to be understood as gases which may not chemically react with exposed surface areas of the material 106. For instance, nitrogen may be considered as an inert gas for the above-specified low-k dielectric material.
As previously explained, depending on whether the corresponding porogen species has been incorporated in the layer 106, further treatment may be performed, typically on the basis of ultraviolet radiation so as to reconfigure the structure of the layer 106, i.e., to reduce the overall material density by creating nano voids and the like. For this purpose, the frequency of the ultraviolet radiation may specifically be selected so as to destroy bonds of the porogen material 107, thereby enhancing volatility of the corresponding components, which may then diffuse out of basic materials, thereby creating nano voids and the like. In other cases, a sufficiently low value for the dielectric constant may be obtained without providing the porogen material 107 on the basis of an appropriate composition of precursor materials. For instance, a dielectric constant of 2.7 and less may be obtained for silicon, oxygen and carbon-containing dielectric materials, which may be formed on the basis of the plasma enhanced CVD process 108.
After the deposition of the low-k dielectric material 106, a plurality of surface defects in the form of particles may be observed, wherein the large number of the corresponding particles may not be compatible with the defect control requirements of sophisticated technology flows, since excessive chemical cleaning of the layer 106 may result in additional damage to exposed surface portions of the layer 106, while less efficient and thus less aggressive cleaning processes may result in an unacceptable defect density.
FIG. 1b schematically illustrates a top view of the substrate 101 and formed thereon the layer 106 as obtained by the plasma enhanced deposition process 108, wherein a typical distribution of unwanted particles is illustrated. As shown, areas of increased particle density 106A may extend across significant surface areas of the layer 106, thereby requiring efficient post-deposition cleaning recipes which, however, may result in a certain degree of surface damage in the layer 106, thereby resulting in reduced performance and reliability of the metallization system of the semiconductor device 100.
Consequently, although plasma enhanced CVD techniques may represent promising techniques for forming low-k dielectric materials and ultra low-k dielectric materials, the high defect rate observed after the deposition may not be compatible with defect control requirements of advanced technology nodes or may result in reduced performance and reliability of respective metallization structures.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.